8088 Assembly Quick Reference

8088 Quick Reference

a compilation of data transfer instructions

─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─
them in memory and registers,Nike Shox Dreams, and transfer data between the input and output ports.
1 General data transfer instructions.
MOV send word or bytes.
MOVSX first sign extension, re-transmission.
MOVZX first zero-expansion, re-transmission.
PUSH the word onto the stack.
POP the word pop up the stack.
PUSHA the AX, CX, DX, BX, SP, BP, SI,Nike Shox Butikk, DI turn onto the stack.
; POPA the DI, SI, BP, SP, BX, DX, CX, AX turn up the stack.
PUSHAD the EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI turn onto the stack.
POPAD to EDI, ESI, EBP, ESP, EBX, EDX, ECX, EAX turn up the stack.
; BSWAP exchange 32-bit registers in the byte order
XCHG ; exchange of words or bytes (at fewest one operand is a register,Nike Shox OZ, not as an operand segment register)
compare and exchange operation CMPXCHG digit. (second operand have to accumulator AL / AX / EAX)
XADD the first interchange and then amass. (results in the 1st operand in)
XLAT word section look-up chart conversion.
─ ─ BX points to a 256 bytes of the table beginning point, AL for the table concordance values ​​(0-255, namely
; 0-FFH); AL to look-up table to return the results. ([BX + AL] -> AL)
2. input Output port transfer instructions.
IN I / O port input (syntax: IN accumulator, port │ DX)
OUT I / O port output (syntax: OUT port │ DX, accumulator)
input and output ports designated by the way now, its range is 0-255; specified by the DX register,
its range is 0-65535.
3 destination residence migrate bid.
LEA Load telling address.
Example: LEA DX, string; to offset deposit to the DX. ;
LDS transfer destination pointer, the pointer is loaded into the DS.
Example: LDS SI, string; the segment address: offset address stored to DS: SI.
LES transfer destination pointer, the pointer is loaded into the ES.
Example: LES DI, string; the segment address: offset address stored to ES: DI.
LFS transfer destination pointer, the pointer is loaded into the FS.
Example: LFS DI,Nike Shox R2, string; the segment address: offset address cached to FS: DI.
LGS transfer destination pointer,Nike Shox Turbo, the pointer is loaded into the GS.
Example: LGS DI, string ;; the segment address: offset deposit to GS: DI.
LSS transfer destination pointer, the arrow is loaded into the SS.
Example: LSS DI, string; the segment address: Offset Address deposit to SS: DI.
4. sign a transfer instruction.
; LAHF flag register transfer, to sign into the AH.
SAHF flag register transfer, the AH is loaded into the flag register.
PUSHF mark stack.
POPF mark stack.
; PUSHD 32 flag onto the stack.
POPD 32 flag stack.
Second, the arithmetic instructions
─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─
ADD addition.
ADC Add with Carry.
INC ; plus 1.
AAA adding of the ASCII code adjustments.
DAA Decimal adjust.
SUB subtraction.
SBB Subtract.
DEC minus 1.
; NEC inverted (0-cut of).
CMP ; comparison (two operands as the subtraction, only the modified flag, do not send back the results).
AAS ; subtraction of the ASCII code corrections.
DAS Decimal adjust. ;
MUL unsigned multiplication.
; IMUL integer multiplication.
these two, send the results back to the AH and AL (byte operation), or DX and AX (word operation),
AAM multiplication ASCII code adjustments.
DIV unsigned division.
IDIV integer division.
these two, the results echo:
affair loopback AL, remainder loopback AH,Nike Shox Norge, (byte operation);
or business loopback AX, remainder loopback DX, (word operation) .
AAD division of the ASCII code to adjust.
; CBW bytes into words. (to sign extension of byte in AL to go to the AH)
CWD Convert word to double word. (the word in AX to DX in to sign extension)
; CWDE word into a double word. (the sign enhancement word in AX to EAX go)
; CDQ double word expansion. (in the words of EAX into EDX go sign extension) ;
three logical instructions
─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─
AND and computing.
OR, or operation.
XOR XOR.
NOT negated.
TEST test (for two operands and operations only modify the flag, do not send back the results). ;
SHL Shift Left Logical.
; SAL arithmetic left. (= SHL)
SHR Logical shift right.
SAR arithmetic right. (= SHR)
ROL Rotate Left.
; ROR Rotate Right.
RCL loop through carry left.
RCR Rotate Right via Carry.
upon 8 kinds of shift instructions, the shift count up to 255 periods.
; shift time, the operation code tin be instantly used, such as SHL AX, 1.
; shift> 1, the frequency shift is given by the CL register.
such as MOV CL, 04
; SHL AX, CL
4 strings Instruction
─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ;
DS: SI source string segment register: source string index.
ES: DI target string segment registers: the target string index
CX recurrence counter.
; AL / AX scan values.
; D symbol 0 method the operation should automatically increment SI and DI; one that ought be auto decrement.
Z flag is accustomed to control the operation of the end of the scan or compare.
; MOVS string displacement.
; (MOVSB ​​transmission character. MOVSW send word. MOVSD transfer twice word.)
CMPS string comparison.
(CMPSB extra characters. CMPSW more words.)
; SCAS string scanning.
to the AL or AX content compared with the target string to compare the results reflected in the flag.
LODS into the string. ;
the source string factor (word or byte) one by one into the AL or AX.
(LODSB transmission character. LODSW ; send word. LODSD transfer double word.)
STOS Save string.
the reverse process is LODS.
; REP if CX / ECX 0 repeat.
REPE / REPZ if ZF = 1 or more are equal, and CX / ECX 0, repeat.
REPNE / REPNZ whether ZF = 0 or not equal comparison, and CX / ECX 0 repeat.
REPC When CF = 1 and CX / ECX 0 repeat.
REPNC When CF = 0 and CX / ECX 0 repeat.
five program branches
─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─
1> unconditional branch (L transfer)
JMP unconditional branch
CALL procedure shriek
RET / RETF process returns.
2> conditional branch instruction (short shift, a distance of -128 to +127)
; (if and only if (SF XOR OF) = 1 时, OP1 interrupt instruction
INT interrupt instruction
INTO overfabsent fromterrupt
IRET Interrupt Return
5> processor control instructions
HLT processor suspended until an interrupt or reset before continuing.
WAIT When TEST is high, the chip guide into the CPU wait state.
; ESC switch to the outer processor.
LOCK blocking bus.
NOP No operation.
STC Set carry flag.
CLC explicit the carry flag.
CMC carry flag counter. ;
STD Set direction flag.
CLD clear direction flag.
STI to set the interrupt enable bit.
CLI Clear disturb enable bit.
VI directive
─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─
DW elucidation of the word (2 bytes).
PROC definition process.
ENDP end of the process.
SEGMENT definition section.
; ASSUME create segment register addressing.
ENDS end of the block.
END end of the process.